1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to an array substrate for an LCD device having a multi-layered metal line.
2. Discussion of the Related Art
Flat panel display (FPD) devices having small size, lightweight, and low power consumption have been a subject of recent research in the coming of the information age. Among many kinds of FPD devices, LCD devices are widely developed and used for notebook and desktop personal computers (PCs) because of their excellent characteristics of resolution, color display and display quality.
Generally, an LCD device includes an upper substrate and a lower substrate facing each other with liquid crystal molecules interposed therebetween. Each substrate has an electrode on an inner surface thereof. An electric field is generated by applying a voltage to the electrodes, thereby driving the liquid crystal molecules to display images depending on light transmittance through the liquid crystal molecules. The lower substrate, which includes thin film transistors (TFTs) to apply a signal to pixel electrodes on the lower substrate, is formed by repeating deposition and patterning steps of a thin film. The upper substrate includes a color filter layer where red (R)/green (G)/blue (B) colors are alternately disposed. The color filter layer can be formed by a dyeing method, a printing method, a pigment dispersion method or an electro-deposition method.
FIG. 1 is a schematic cross-sectional view of a related art liquid crystal display device. As shown in FIG. 1, first and second substrates 21 and 71 face and are spaced apart from each other. A gate electrode 23 of a conductive material such as metal is formed on an inner surface of the first substrate 21 and a gate insulating layer 29 of silicon nitride (SiNx) or silicon oxide (SiO2) covers the gate electrode 23. An active layer 31 of amorphous silicon is formed on the gate insulating layer 29 over the gate electrode 23 and an ohmic contact layer 33a and 33b of impurity-doped amorphous silicon is formed on the active layer 31. Source and drain electrodes 41 and 43 of a conductive material such as metal are formed on the ohmic contact layer 33a and 33b. The source and drain electrodes 41 and 43 constitute a thin film transistor (TFT) “T” with the gate electrode 12. A passivation layer 51 of SiNx, SiO2 or organic insulating material is formed on the source and drain electrodes 41 and 43. The passivation layer 51 has a drain contact hole 53 therethrough exposing the drain electrode 43. A pixel electrode 61 of a transparent conductive material is formed on the passivation layer 51 at a pixel region (not shown) and connected to the drain electrode 43 through the drain contact hole 53.
A black matrix 73 corresponding to the TFT “T” is formed on an inner surface of the second substrate 71. The black matrix 73 prevents a light leakage of an exterior of the pixel electrode 61 and a photo current generation by shielding light from being incident on a channel of the TFT “T.” A color filter layer 75a and 75b having alternating colors of red (R), green (G) and blue (B) is formed on the black matrix 73. Here, one color of the color filter layer 75a and 75b corresponds to one pixel region (not shown). A common electrode 77 of a transparent conductive material is formed on the color filter layer 75a and 75b. 
A liquid crystal layer 81 is interposed between the pixel electrode 61 and the common electrode 77.
Here, the first substrate 21 is referred to as an array substrate and illustrated in FIG. 2.
FIG. 2 is a schematic plan view of an array substrate for a related art liquid crystal display device. As shown in FIG. 2, thin film transistors (TFTs) “T” in a matrix are formed on a substrate 21, referred to as an array substrate. The TFTs act as switching devices. Each TFT “T” includes a gate electrode 23, an active layer 31 over the gate electrode 23, and source and drain electrodes 41 and 43. Moreover, each TFT “T” is connected to a gate line 25 and a data line 45. A gate pad 27 wider than the gate line 25 is formed at one end of the gate line 25 and a data pad 49 wider than the data line 45 is formed at one end of the data line 45. A gate pad terminal 63 and a data pad terminal 65, which are input means of an external signal, are connected to the gate pad 27 and the data pad 49, respectively. Here, a pixel region “P” is defined by the gate line 25 and the data line 45. A storage capacitor “C” is formed over a portion of the gate line 25 and connected in parallel to a transparent pixel electrode 61 of the pixel region “P.” The storage capacitor “C” uses the portion of the gate line 25 as a first capacitor electrode and a source-drain metal layer 47 as a second capacitor electrode. The source-drain metal layer 47 of the same material as the drain electrode 43 is disposed over the portion of the gate line 25 and connected to the pixel electrode 61 through a capacitor contact hole 55.
FIG. 3 is a schematic cross-sectional view taken along the line III-III of FIG. 2. As illustrated in FIG. 3, a gate electrode 23, a gate line 25 and a gate pad 27 at one end of the gate line 25 are formed on a substrate 21. A gate insulating layer 29, i.e., a first insulating layer, is formed on an entire surface of the substrate 21. An active layer 31 and an ohmic contact layer 33 of an island shape are formed on the gate insulating layer 29 over the gate electrode 23. Source and drain electrodes 41 and 43 contacting the ohmic contact layer 33 are formed on the ohmic contact layer 33. A data line 45 is connected to the source electrode 41 and a data pad 49 is formed at one end of the data line 45. A source-drain metal layer 47 of an island shape is formed over a portion of the gate line 25. Here, the data line 45, and the source and drain electrodes 41 and 43 have a single layer of chromium (Cr) or molybdenum (Mo). A passivation layer 51, i.e., a second insulating layer, is formed on the data line 45, and the source and drain electrodes 41 and 43. A drain contact hole 53 is formed through the passivation layer 51. A transparent pixel electrode 61 is formed on the passivation layer 51 and connected to the drain electrode 43 through the drain contact hole 53.
When the data line 45 having a single layer of Cr or Mo are used for a large size substrate, images of a uniform display quality cannot be obtained over an entire surface of a liquid crystal panel due to a high resistance of the Cr or Mo. Accordingly, the size of the substrate may be limited. As a resistance of the data line 45 becomes lower, signals flow better through the data line 45, and the data line 45 is more suitable for a large size substrate. Therefore, it is necessary to form the data line 45 out of a low resistance material. Generally, an aluminum (Al) line is used as a low resistance line. However, since the Al line is susceptible to chemicals, and hillock formation often occurs in the Al line, a single layer of aluminum has some disadvantages. Therefore, a data line 45 having a triple layer such as Mo/Al/Mo is suggested.
FIGS. 4A to 4E are schematic cross-sectional views illustrating a fabricating process of an array substrate using a triple layer. FIGS. 4A to 4E are also taken along a line III-III of FIG. 2.
In FIG. 4A, a gate electrode 23, a gate line 25 and a gate pad 27 at one end of the gate line 25 are formed on a substrate 21. Generally, the gate electrode 23, the gate line 25 and the gate pad 27 have a double layer including aluminum (Al). For example, Al may be used as a first metal layer, and Mo or Cr may be used as a second metal layer. Even though aluminum has low resistance, aluminum is susceptible to chemicals and line defect due to a hillock occurring during a subsequent high temperature process. Accordingly, Mo or Cr having high corrosion resistance is used as the second layer on the first layer. A gate insulating layer 29, i.e., a first insulating layer, is formed on an entire surface of the substrate 21. The gate insulating layer 29 has one of an inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiO2). An active layer 31 and an ohmic contact layer 33 of an island shape are formed on the gate insulating layer 29 over the gate electrode 23. The active layer 31 and the ohmic contact layer 33 include intrinsic amorphous silicon (a−Si:H) and impurity-doped amorphous silicon (n+a−Si:H), respectively.
In FIG. 4B, a first metal layer 35 of Mo, a second metal layer 37 of Al and a third metal layer 39 of Mo are sequentially formed on an entire surface of the substrate 21. The first metal layer 35 is used to prevent a spiking in which the second metal layer 37 penetrates the active layer 31 or the ohmic contact layer 33. The third metal layer 39 is used to reduce a contact resistance between the second metal layer 37 and a pixel electrode (not shown) of a subsequent process.
In FIG. 4C, source and drain electrodes 41 and 43, a data line 45 and a data pad 49 are formed through patterning a triple layer of the first, second and third metal layers 35, 37 and 39. The source and drain electrodes 41 and 43 are spaced apart from each other. The source electrode 41 is connected to the data line 45, and the data pad 49 is disposed at one end of the data line 45. At the same time, a source-drain metal layer 47 of an island shape is formed on the gate insulating layer 29 over a portion of the gate line 25. Sequentially, the active layer 33 is exposed through etching the ohmic contact layer 33 between the source and drain electrodes 41 and 43.
In FIG. 4D, a passivation layer 51, i.e., a second insulating layer, is formed on an entire surface of the substrate 21. The passivation layer 51 has a drain contact hole 53 therethrough exposing the drain electrode 43, a gate pad contact hole 57 exposing the gate pad 27, a data pad contact hole 59 exposing the data pad 49 and a capacitor contact hole 55 exposing the source-drain metal layer 47.
In FIG. 4E, a pixel electrode 61 is formed on the passivation layer 51 through deposing and patterning one of a transparent conductive metal group including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). The pixel electrode 61 is connected to the drain electrode 43 and the source-drain metal layer 47.
However, when a triple layer is applied to source and drain electrodes and a data line, a metal residue causing an inferiority of an LCD device remains during depositing and patterning process of three metal layers. These problems will be illustrated in FIGS. 5A to 6C.
FIGS. 5A to 5D are schematic cross-sectional views illustrating a metal residue generation of three metal layers, and FIGS. 6A to 6C are scanning electron microscope (SEM) images showing a surface state according to a step of a patterning process.
In FIG. 5A, first, second and third metal layers 35, 37 and 39 are sequentially formed on a substrate 21 including a gate line 23 and a gate insulating layer 29 by using a sputtering method. Here, since the first metal layer 35 has a thickness less than about 100 Å, the first metal layer 35 has pinholes at a step portion “A” of the gate insulating layer 29. Accordingly, when the second metal layer 37 is deposited on the first layer 35, the second metal layer 37 is diffused into the first metal layer 35 through the pinholes at the step portion “A.” Next, the first, second and third metal layers 35, 37 and 39 are patterned to form source and drain electrode (not shown) and a data line (not shown) through a photolithographic process using a photoresist (PR) pattern (not shown) as an etching mask.
In FIG. 5B, the third and second metal layers 37 and 39 are etched. Here, since the second metal layer 37 is diffused into the first metal layer 35 at the step portion “A” during the depositing process, the second metal layer 37 of the step portion “A” is not eliminated. Accordingly, the first and second metal layers 35 and 37 coexist at the step portion “A.” This surface state after etching the second metal layer 37 is shown in FIG. 6A.
In FIG. 5C, the first metal layer 35 is etched. However, since the first and second metal layers 35 and 37 coexist at the step portion “A,” the first metal layer 37 of the step portion “A” is not eliminated. This etching result is referred to as an under etch. This surface state after etching the first metal layer 35 is shown in FIG. 6B.
In FIG. 5D, after an ohmic contact layer (not shown) between the source and drain electrodes (not shown) is etched, the PR pattern is removed. Here, the gate insulating layer 29 is slightly etched. However, even after the ohmic contact layer (not shown) is etched, the first and second metal layers 35 and 37 of the step portion “A” are not eliminated and remain. This surface state after etching the ohmic contact layer (not shown) is shown in FIG. 6C. These coexisting first and second metal layers 35 and 37 of the step portion “A” are referred to as a metal residue. The metal residue causes inferiority such as a point defect or a spot in subsequent processes.
On the other hand, the first, second and third metal layers for the source and drain electrodes and the data line are etched with a mixed acid solution at a time. However, a galvanic phenomenon (electro-chemical reaction) occurs due to the mixed acid solution during the etching process. As the first and third layers become thicker, the galvanic phenomenon affects much more. Specifically, as the first metal layer is thicker than the third metal layer, the second metal layer is more over-etched. Accordingly, a sidewall of the triple layer has an inverse taper shape. This phenomenon will be explained with respect to FIG. 7.
FIG. 7 is a magnified cross-sectional view of a portion “D” of FIG. 4D. As shown in FIG. 7, a second metal layer 37 of Al between first and third metal layers 35 and 39 of Mo is over-etched. Accordingly, when a passivation layer 51 is formed on an entire surface of the substrate (not shown), the passivation layer 51 does not completely cover the second metal layer 37 due to the inverse taper shape “E” of the sidewall.